ABC: System for Sequential Logic Synthesis and
Formal Verification, https://github.com/berkeley-abc/abc/,this
system is maintained by Dr. Alan Mishchenko
alanmi@berkeley.edu.
The EPFL Logic Synthesis Libraries,
https://github.com/lsils/lstools-showcase,
the EPFL logic synthesis libraries are a collection of
modular open source C++ libraries for the development of
logic synthesis applications, which is maintained by
Prof. Giovanni De Micheli's group in EPFL.
yosys - Yosys Open SYnthesis Suite ,
https://github.com/YosysHQ/yosys,
this is a framework for RTL synthesis tools. It
currently has extensive Verilog-2005 support and
provides a basic set of synthesis algorithms for various
application domains, which is maintained by Claire
Wolf.
Advanced Logic Synthesis and Optimization tool
(ALSO), https://gitee.com/zfchu/also/,
ALSO is based on the EPFL Logic Synthesis Libraries, the
aim is to exploit advanced logic synthesis tools for
both modern FPGA and emerging nanotechnologies,
maintained by Prof. Zhufei Chu's group in Ningbo
University.
UNIVR Logic Synthesis Software, https://jackhack96.github.io/logic-synthesis/,
The purpose of this site is to host source code,
binaries and documentation of software for combinational
and sequential logic synthesis. Currently, the following
libraries are made available: Espresso, SIS, MVSIS and
BALM.
The software has been updated to make it compliant with
current compilers. More specific information is
available
in the pages of each tool. The site is maintained by
Matteo
Iervasi and Prof. Tiziano Villa in University of Verona.